clear(print_given). set(binary_res). set(para_into). clear(detailed_history). clear(print_kept). clear(print_back_sub). assign(max_seconds,10). assign(stats_level,0). % This corresponds to the knowledge in Section 8.4. % I use u, u1, u2, ... for gates, % x, x1, x2, ... for terminals, % and y, y1, y2, ... for signals list(usable). % if x1 is connected to x2, then they have the same signal -connected(x1,x2) | signal(x1) = signal(x2). % all signals are either 1 or 0 signal(x) = 1 | signal(x) = 0. 0 != 1. y = y. % if x1 is connected to x2, then x2 is connected to x1 -connected(x1,x2) | connected(x2,x1). % the output of an OR is 0 iff % both of its two inputs are 0. type(u) != OR | signal(in1(u)) != 1 | signal(out(u)) = 1. type(u) != OR | signal(in2(u)) != 1 | signal(out(u)) = 1. type(u) != OR | signal(in1(u)) != 0 | signal(in2(u)) != 0 | signal(out(u)) = 0. % the output of an AND is 1 iff % both of its two inputs is 1 type(u) != AND | signal(in1(u)) != 0 | signal(out(u)) = 0. type(u) != AND | signal(in2(u)) != 0 | signal(out(u)) = 0. type(u) != AND | signal(in1(u)) != 1 | signal(in2(u)) != 1 | signal(out(u)) = 1. % the output of an XOR is 1 iff % its inputs are different type(u) != XOR | signal(in1(u)) != signal(in2(u)) | signal(out(u)) = 0. type(u) != XOR | signal(in1(u)) = signal(in2(u)) | signal(out(u)) = 1. % gates in the circuit type(exor1) = XOR. type(exor2) = XOR. type(and1) = AND. type(and2) = AND. type(or1) = OR. % the connections using b1, b2, b3 as inputs, and add and carry as outputs connected(b1,in1(exor1)). connected(b2,in2(exor1)). connected(b1,in1(and1)). connected(b2,in2(and1)). connected(out(exor1),in1(exor2)). connected(b3,in2(exor2)). connected(b3,in1(and2)). connected(out(exor1),in2(and2)). connected(out(and1),in1(or1)). connected(out(and2),in2(or1)). connected(out(exor2),add). connected(out(or1),carry). % a test case signal(b1) = 1. signal(b2) = 0. signal(b3) = 1. end_of_list. list(sos). % prove that add = 0 and carry = 1 % signal(add) = 1. signal(carry) = 0. end_of_list.