Avnet Xilinx Virtex-II Pro Configuration III

The purpose of Configuration III is to test Gigabit Ethernet with Xilinx Micro-Kernel (XMK). Except the Gigabit Ethernet, the rest settings are similar to the Configuration II.

In this configuration, the following hardware cores are configured:

• Sysace: controller for compact Flash card
  
• SDRam (32M): a Mux is added for the SDRam module that shares I/O buses with Sysace.
  
• GEMac 1000M: Ethernet controller
  
• Simple Matcher: a hardware core designed based on the paper, C. D. Lo, “Hardware-Assisted Network-Based Intrusion Detection,” in the International Conference on Informatics, Cybernetics and Systems, December 14-16, 2003, Kaohsiung, Taiwan.
  

This figure shows the schemetic diagram for the hardware components hooked in the system. Note that all design and programs are associated to ppc405_0. The ppc405_1 is not used. The mii_clock_management_0 is used to control the special timing for the Gigabit Ethernet core.

This figures shows the addressing and size of all hardware components.

The project also includes a set of test programs to test each of the memory and peripheral components running on a standalone O.S. In order to get this configuration working, the following requirements must be strictly followed.

• Board jumpers: Since all memory modules except DDR SDRam (120M) are controlled by Spartan II 300E. Thus, it has to be "pass_thru.mcs." Jumper settings, especially for Sysace to get "locking" errors if jumpers are not set properly, are as follows:
  • JP8: open (for boundary scan)
  • JP9: open (for master-serial mode)
  • S2 d1: on (reload mode)
  • S1 d4: on (CFG mode)
• Core licenses: Except Emac, all cores are free. Users have to obtain a license for Emac from Xilinx and install it in the directory .Xilinx under the root directory. The Simple Matcher core can be obtained from this site. It has to be unzipped to the root director such drive c:/ before the project can be opened.

Hardware recompilation is not necessary and sometimes may cause problems. We do not suggest recompile the hardware unless there is a need. Applications, however, can be recompiled without any problems. The following steps show how to unpack and experiment this project ball.

• Download the Simple Matcher core and unzip it to the root directory. Once done, your will have a directory edk_user_repository under the root directory.
• Download the project zipped ball and unzip it to a directory where you remember for later access.
• Start Xilinx Platform Studio 8.2i (you have to have the identical version of the identical software) and open the project file "system.xmp." in the directory where you unzipped the project ball.
• Start a hyper terminal with the settings: 115200bps/ 8/ N/ 1/ no flow control. Note that you will have to connect COM1 to JS1 port on board. All standard I/O will be redirected through RS232 and will be shown on the hyper terminal.
• Connect a Xilinx Parallel Cable IV (DLC7) from Parallel port to JP12 on board. This cable is used to reconfigure the chips, load programs to the board, and debug programs.
• Use Xilinx iMPACT to reconfigure Virtex-II Pro chip
• Use XMD in Xilinx Platform Studio 8.2i to load programs: Debug -> Launch XMD...

The aforementioned procedures only give you an idea about how to redo the experiment. For more detailed information, you should reference to Avnet and Xilinx documents.