Improving Microarchitectural Performance with Neural Predictors

Abstract

Microprocessors predict the near-term behavior of a program so that work on future instructions may begin early, reducing the amount of time the program takes to run. These predictions must be highly accurate. Borrowing concepts from neuroscience, we will explore the use of artificial neurons to replace the predictors used today. Artificial neurons have been used as predictors in other domains, and preliminary results show that they work well for predicting program behavior. We will improve these results by exploring ways to make the neurons work faster, more accurately, and with a larger scope, thus improving overall performance of computers.

This project will explore the use of neural learning in microarchitectural predictors such as branch predictors. Neural branch predictors replace commonly used counter-based techniques with neural learning, providing better predictive capabilities. Special emphasis will be placed on reducing the latency of neural predictors, which hinders their contribution to overall performance. We expect the following results: (1) improved accuracy for neural predictors, (2) decreased impact of neural predictor latency on performance, (3) a deeper understanding of the properties of the branch prediction problem that are exploited by neural predictors, and (4) new digital circuits for implementing neural predictors in microarchitectures.

Funded by NSF's Computer Systems Architecture program (CSA), grant #0311091, for three years beginning in 2003.

P.I.: Daniel A. Jiménez