Cray architecture simulator: In 1985 the UT System signed an agreement with Cray Research to buy a large Cray Supercomputer for the UT System High Performance Computing Center. As part of that program, Cray Research agreed to fund a program of small grants to faculty so that they could develop applications to use this computer. Steve Robbins and I applied for a grant to develop materials to teach about the Cray XMP architecture. The result of this was a cycle-accurate simulator and the following book:
K. A. Robbins and S. Robbins (1989)
The Cray X-MP: A Case Study in Pipelined Architecture and Vector Processing
Springer-Verlag Lecture Notes in Computer Science #374.
I taught the graduate computer architecture using the material we developed. Along the way we also did some research on the Cray memory architecture and published some papers: including:
K. A. Robbins and S. Robbins (1995)
Buffered banks in multiprocessor systems
IEEE Trans on Computers, 44(4):518-530.
As a high point, Steve and I were invited to Chippewa Falls, Wisconsin to present our work. The memory architects of the Cray XMP came to our talk and discussed the architecture with us.
Mic1 simulator for understanding the instruction cycle (1996 to 1998) A number of years later, Steve Robbins and I worked on a simulator for the Mic1, the hypothetical microprocessor used in the Tanenbaum book on Computer Organization. Steve wrote the simulator and I developed the curriculum materials and taught them in a course. This work is described in a paper that appeared in the IEEE Transactions on Education: A microprogramming animation.
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