Submission Deadlines:
In this class, you have been writing the compiler for a toy programming language, TL05. At this point your compiler should be able to parse the TL05 language, type check it, generate an ILOC-based intermediate representation (IR) in SSA Form, and possibly perform optimizations on that IR. The final stage of the project will be to add a compiler back-end that generates MIPS assembly code.
You may choose C, C++, or Java to implement your compiler, but it must compile and run on the machines in the Computer Science Department's Linux lab. (If you choose C or C++, you will also need to create a makefile that will build an executable from your source files.) The entire compiler must be your own, independent work.
The fourth assignment is to write a back-end for your compiler. This back-end needs to:
Translating out of SSA Form is probably best done after optimization prior to instruction selection. The general procedure for compiling out of SSA Form is described in Section 9.3.5 of Engineering a Compiler. Additional references include: Morgan, Building an Optimizing Compiler (1998), Section 7.3; and Rastello, et al., Optimizing Translation Out of SSA Using Renaming Constraints; and Briggs et al., Practical improvements to the construction and destruction of static single assignment form. For TL05, the biggest potential problem that naive copy insertion cannot handle is the "swap" problem.
The ILOC and MIPS instruction sets are quite similar, and depending on the subset of ILOC which the IR contains, instruction selection may be done through a simple 1:1 substitution of MIPS instructions for ILOC instructions. (Please refer to Appendix A of Computer Organization and Design: The Hardware/Software Interface for a description of the MIPS Instruction Set Architecture (ISA), the MIPS assembly language, and the SPIM simulator.) It may be necessary, however, to do handle some instructions in a slightly more complicated manner. (For example, the MIPS load-from-memory instruction takes a "register + a 16 bit constant offset" as its address, and it is not possible to map ILOC's loadAO instruction directly to it.) You may wish to use an instruction selection scheme based on the peephole optimization to handle these cases. (C.f., Section 11.4 of Engineering a Compiler, but you can probably simplify the scheme described there.)
In order to generate executable MIPS code, however, you will have to generate code that uses only those registers available in the MIPS ISA. Normally this would be done using graph-coloring register allocator with spilling; implementing this will be extra credit.
In order to get executable code without a register allocator, you can add a "dummy register allocator pass" that simply sets aside dedicated registers for the input and output of each MIPS instruction, and creates one global variable (in the ".data" segment or as an offset from the frame pointer) for each IR temporary. You would then place a store instruction to write to that global variable, each time it the temporary is assigned to, and place load instructions to transfer the data back from the global variables into the dedicated registers for each MIPS instruction. This implementation would be quite inefficient, but it will produce correct code.
The final output of your compiler should be an ASCII text file executable by the SPIM MIPS Simulator.
When you have completed your assignment, you should create a tar archive or zip file containing your source files (with the correct package-based directory structure if you're using Java), the makefile (if your compiler is in C or C++), and your test cases. These should be attached to an email to vonronne@cs.utsa.edu. The subject of this email should containing the text "CS 5363 Submission #3", and the body should contain a "cover letter". This "cover letter" must contain:
This assignment has two due dates. You may turn in the current state of your compiler by the first due date, at which time you will be given suggestions for further improvements. Your first submission will not, however, be graded until the second deadline. If you wish to implement register allocation (which will be extra credit), you should attempt to finish this part by the first due date.
As a matter of policy, late work will not be accepted. Partially completed assignments will, however, be evaluated for partial credit. This assignment depends on the previous parts of the compiler working correctly, so the correctness or incorrectness of the rest of the compiler may be considered when grading this assignment. Projects will be evaluated using a rubric similar to the following:
In addition, extra credit will be given for deficiencies in the parser, type checker, SSA construction, and optimizations that have been remedied since part #3 was turned in. A penalty of up to 50% may be deducted if the program doesn't compile and run on the machines in the department's Linux lab.
There may need to be corrections, clarifications, or other modifications to these instructions, you are responsible for monitoring the class web site, monitoring your CS account mailboxes, and listening during lecture for announcements related to this assignment.