Deadline: 1pm, Wednesday, November 21, 2007
In this class, you have been writing the compiler for a toy programming language, TL07. At this point your compiler should be able to parse the TL07 language, type check it, generate an ILOC-based intermediate representation (IR), and possibly perform optimizations on that IR. The fourth and last required stage of the project will be to add a compiler back-end that generates MIPS assembly code.
This back-end needs to:
The ILOC and MIPS instruction sets are quite similar, and depending on the subset of ILOC which the IR contains, instruction selection may be done through a simple 1:1 substitution of MIPS instructions for ILOC instructions. (Please refer to Appendix A of Computer Organization and Design: The Hardware/Software Interface for a description of the MIPS Instruction Set Architecture (ISA), the MIPS assembly language, and the SPIM simulator.) It may be necessary, however, to handle some instructions in a slightly more complicated manner. (For example, the MIPS load-from-memory instruction takes a "register + a 16 bit constant offset" as its address, and it is not possible to map ILOC's loadAO instruction directly to it.) Note: SPIM provides simulated system calls for printing out characters, you may find the read_int, print_int, and print_char system calls useful for implementing TL07's READINT and WRITEINT operations. You may wish to use an instruction selection scheme based on the peephole optimization to handle these cases. (C.f., Section 11.4 of Engineering a Compiler, but you can probably simplify the scheme described there.)
In order to generate executable MIPS code, however, you will have to generate code that uses only those registers available in the MIPS ISA. Normally this would be done using graph-coloring register allocator with spilling; implementing this will be extra credit.
In order to get executable code without a register allocator, you can add a "dummy register allocator pass" that simply sets aside dedicated registers for the input and output of each MIPS instruction, and creates one global variable (in the ".data" segment or as an offset from the frame pointer) for each IR temporary. You would then place a store instruction to write to that global variable, each time it the temporary is assigned to, and place load instructions to transfer the data back from the global variables into the dedicated registers for each MIPS instruction. This implementation would be quite inefficient, but it will produce correct code.
The final output of your compiler should be an ASCII text file executable by the SPIM MIPS Simulator. This file name should have the extension ".s" appended to the input file stem. The compiler should also continue to output the parse tree, AST, and CFG. So if the input file name "simple.tl07", the parse-tree should be placed in "simple.pt1.dot", the AST should be placed in "simple.ast.dot", the CFG/ILOC output should be placed in "simple.cfg.dot", and the MIPS assembly code should be placed in "simple.s".
Please see revised packaging and submission instructions.
Please see revised grading notes.
There may need to be corrections, clarifications, or other modifications to these instructions, you are responsible for monitoring the class web site, monitoring your CS account mailboxes, and listening during lecture for announcements related to this assignment.