Lab 7

Assigned : 03/28 (CS2511.001)                  03/30 (CS2511.002)

Due : 04/04 (CS2511.001)           04/06(CS2511.002)

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Objectives

• Learn the function of flip-flop.
• Analyze the operation of D flip-flop and verify using timing diagram.
• Test your design using Logicworks.

Resources

Unit 11 from the textbook.
Contact the TA if you have any questions.

Problem Description

The following figure is a falling-edge triggered D flip-flop. This flip-flop consists of two basic S-R latches with added gates. When the clock input (CK) is 1, the value of D is stored in the first S-R latch (P). When the clock changes from 1 to 0, the value of P is transferred to the output latch (Q). Thus, the operation is similar to that of the master-slave S-R flip-flop, except for the edges at which the data is stored. Initially CK = 0 and D = 0. CK changes its value every 20 ns. D changes to 1 at time 30 ns, and changes to 0 at time 50 ns. The timing diagram for CK and D is shown below.(You can download sample timing file , but you still need to change the values inside)

 

You should do the following steps: (total 30 pts)

• Draw the circuit (5pts) above  and its timing diagram (10 pts) in Logicworks5 (total simulation time = 90 ns, delay for all gates is 1 ns). Print out the circuit and its timing diagram.
• Analyze the timing diagram to find all possible values for CK, D, P, S, R, Q and verify if the condition is stable. You need to fill out a table like the table given below, using the values shown in the timing diagram (15 pts).

CK	D	P	S	R	Q	stable/unstable
0	0	0	0	1	0	stable
1	0	0	0	1	0	unstable
1	0	0	.	.	.	.
.	.	.	.	.	.	.
.	.	.	.	.	.	.

Hand-in Requirements (Deliverables)

Staple all your hand-ins as required in problem description to form a single packet. Write your name, course and  recitation section number on the front.