- A language for
describing the structural, physical and behavioral characteristics of digital
systems.
- Execution of a
VHDL program results in a simulation of the digital system.
- Allows us to
validate the design prior to fabrication.
- The definition
of the VHDL language provides a range of features that support simulation of
digital systems.
- VHDL supports both
structural and behavioral descriptions of a system at
multiple levels of abstraction.
- Structure and
behavior are complementary ways of describing systems.
- A description of
the behavior of a system says
nothing about the structure or the components that make up the system.
- There are many
ways in which you can build a system to provide the same behavior.
- Reference: "VHDL
Starter's Guide", Sudhakar Yalamanchili, Prentice Hall
- VHDL allows you to
specify:
- The
components of a circuit.
- Their
interconnection.
- The
behavior of the components in terms of their input and output signals.
- What are its
behavioral properties of the half-adder circuit ?
- The event on a
, from 1 to 0, changes the outputs after a 5ns propagation delay.
- Both gates (and
wires) have inertia or a natural resistance to change.
- A third property
of this circuit is concurrency.
- Both the
xor and and gate compute new output values
concurrently when an input changes state.
- These new events
may go on to initiate the computation of other events in other parts of the
circuit, e.g. s1 and s3 .
- Data driven
system : Events on signals lead to computations that may
generate events on other signals.
- We can view VHDL
as a programming language for describing the generation of events in digital
systems supported by a discrete event simulator
.
- A discrete event simulator executes VHDL
code, modeling the passage of time and the occurrence of events at various
points in time.
- It maintains an
event list data structure to keep track of the order of all future events in
the circuit.
- Advance simulation
clock to time of next event, update signals receiving values.
- Evaluate all
components affected by signal updates and schedule new events.
- Signals
: Like variables in a programming language such as C, signals
can be assigned values, e.g., 0, 1, Z.
- However, signals
also have an associated time value .
- A signal
receives a value at a specific point in time and retains that value until it
receives a new value at a future point in time.
- The sequence of
values assigned to a signal over time is the waveform of the signal.
- A variable always
has one current value.
- At any instant in
time, a signal may be associated with several time-value pairs.
- Design entity: A
component of a system whose behavior is to be described and simulated.
- Two components to
the description:
- The interface to
the design: entity declaration.
- The internal
behavior of the design: architecture construct.
- Entity example for
half adder:
- half_adder
is the name given to the design entity.
- The input and
outputs signals; a , b , sum and carry , are
referred to as ports .
- Each port has a
type, bit and bit_vector can assume values of 0 and
1.
- Each port has a
mode; in , out or inout (bidirectional signals).
- Bit vectors are
specified as:
- A and B are 32 bits
long with the most significant bit as 31.
- A more general
definition of bit and bit_vector are std_logic and std_logic_vector , which can assume more
than just 0 and 1.
- Concurrent
statements :
- Signal
assignment statements specify the new value and the time at which the signal
is to acquire this value.
- The textual
order of the concurrent signal assignment statements (CSAs) do NOT effect
the results.
- We can also use
(local) signals internal to the architecture, e.g., s1 , s2 and s3 in the full
adder circuit.
- The following
statements are also legal:
- A driver list that specifies a
waveform.
- This statement
generates a set of transactions (time-value pairs) to be carried out at distinct times in the
future.
- Conditional
Signal Assignment Statement :
- The first
conditional found to be true determines the value transferred to the
output.
- The Selected Signal Assignment Statement behaves similarly.
- Processes are
used:
- For
describing component behavior when they cannot be simply modeled as delay
elements.
- To
model systems at high levels of abstraction.
- Process
incorporate conventional programming language constructs.
- A process is a
sequentially executed block of
code, which contains.
- arrays
and queues.
- Variable assignments, e.g., x := y , which, unlike
signals, take effect immediately.
- if-then-else and
loop statements to control flow.
- Signal
assignments to external signals.
- Processes contain
sensitivity lists in which
signals are listed, which determine when the process executes.
- In reality, CSAs
are also processes without the process , begin and
end keywords.
- Looping constructs
include the for and while statements, e.g.,
- The loop index is implicitly declared, local to
the loop and cannot be changed.
- Processes are
executed once upon initialization.
- Thereafter, they
are executed in a data-driven manner by either:
- an
event on one or more signals in the sensitivity
list .
- waiting for the occurrence of specific event using a wait statement.
- The wait statement specifies the conditions
under which a process may resume execution after being suspended, e.g.,
- wait for
time expression ; -- wait for a specified time interval.
- wait on
signal ; --
wait on a signal(s).
- wait until
condition ;
-- wait until condition becomes true;
- The first and
third form allow processes to model components that are not necessarily data
driven.
- wait statements also allow processes to suspend at multiple points,
and not just at the beginning.
- For example, a
positive edge-triggered flip-flop:
- Note attribute
Clk ' event which is true when an event (rising
or falling edge) occurs on signal Clk .
- A D flip-flop with
asynchronous reset (R) and set (S) inputs given in reference.
- A state machine
(Mealy machine):
- Combinational part
implemented in one process, sensitive to events on the input signals or state
variables.
- Sequential part
implemented in a second process, sensitive to the rising edge of the
clock.
- Structural model:
A description of a system in terms of the interconnection of its components,
rather than a description of what each component does.
- A structural model
does NOT describe how output events are computed in response to input
events.
- How do we simulate
the circuit ?
- Behavioral
models of each component are assumed to be provided.
- A VHDL structural
description must possess:
- The
ability to define the list of components.
- The
definition of a set of signals to be used to interconnect them.
- The
ability to uniquely label (distinguish between) multiple copies of the same
component.
- A structural
description of a full adder:
- A state machine of
a bit-serial adder:
- A structural
description of a bit-serial adder:
