Preparing the Makefile:

A make file consists of a series of entries of the following form

[...targetfile..]:              [.....dependencies....]
[One Tab Space]                 [.....commands........]

The first line of each entry is a list of targetfiles separated by spaces, then a colon and then a list of files called the dependencies. A dependency is a file which if changed will alter the functionality of the target file. The colon is followed by a tab before any text is inserted. If the names of the dependencies overflow in the next line then that list is followed by a semi-colon before starting the commands.

A typical Makefile for our running example of main.c and average.c is as given below

 
average: main.o average.o

		         cc -o average main.o average.o  -lm

main.o:  main.c

		         cc -c main.c

average.o:  average.c

		         cc -c average.c

The make program interprets the first entry in the following manner: average is the target file and it depends on main.o and average.o and it is obtained by executing the command on the next line. The other two entries are interpreted in the same manner. An example of a Makefile is given along with the example programs. Hence the make utility proposes the following methodology.... ...edit...make...run and repeat...